1.72 GB | 8min 16s | mp4 | 1280X720 | 16:9
Genre:eLearning |Language:English
Files Included :
1 Course Overview.mp4 (4.14 MB)
10 Components of Register model P2.mp4 (6.71 MB)
11 Components of Register model P3.mp4 (6.78 MB)
13 Typical Learning Path.mp4 (7.44 MB)
14 Understanding different types of registers.mp4 (5.78 MB)
15 Implementation of Register in Verification Environmnet P1.mp4 (48.5 MB)
16 Implementation of Register in Verification Environmnet P2.mp4 (53.63 MB)
17 Alternate way of adding configure function.mp4 (3.25 MB)
18 Summary Configure function.mp4 (4.56 MB)
19 Implementation of Register in Verification Environmnet P3.mp4 (20.76 MB)
2 Agenda.mp4 (6.14 MB)
22 Adding Register with two fields.mp4 (36.86 MB)
24 Adding Register with reserved bits.mp4 (19.39 MB)
26 Different Access Policy P1.mp4 (5.13 MB)
27 Different Access Policy P2.mp4 (55.58 MB)
28 Different Access Policy P3.mp4 (43.54 MB)
29 Different Access Policy P4.mp4 (50.73 MB)
3 Advantage of UVM RAL P1.mp4 (11.98 MB)
31 Adding Memory P1.mp4 (3.69 MB)
32 Adding Memory P2.mp4 (31.41 MB)
4 Advantage of UVM RAL P2.mp4 (7.67 MB)
5 Advantage of UVM RAL P3.mp4 (4.07 MB)
6 Advantage of UVM RAL P4.mp4 (4.76 MB)
7 When to use RAL in Verification environment.mp4 (22.26 MB)
9 Components of Register model P1.mp4 (27.05 MB)
1 Agenda.mp4 (622.66 KB)
2 Adding Register Block P1.mp4 (12.36 MB)
3 Adding Register Block P2.mp4 (18.16 MB)
4 Adding Register Block P3.mp4 (59.01 MB)
1 Agenda.mp4 (3.12 MB)
10 Adapter code with Protocol Specific ports P1.mp4 (23.76 MB)
11 Adapter code with Protocol Specific ports P2.mp4 (4.46 MB)
12 Summary.mp4 (8.02 MB)
2 Usage of adapter.mp4 (2.16 MB)
3 Typical flow.mp4 (2.85 MB)
4 Structure of uvm reg bus op struct.mp4 (3.17 MB)
5 Complete flow.mp4 (7.02 MB)
6 Understanding reg2bus.mp4 (35.07 MB)
7 Understanding bus2reg.mp4 (4.35 MB)
8 Adapter code with native memory ports P1.mp4 (12.6 MB)
9 Adapter code with native memory ports P2.mp4 (14.68 MB)
1 Agenda.mp4 (1.98 MB)
10 Adding Agent.mp4 (2.88 MB)
11 Adding Register Model.mp4 (44.04 MB)
12 Adding env + uvm test top + testbench top.mp4 (15.58 MB)
13 Executing Code.mp4 (13.13 MB)
15 Understanding Desired and Mirrored Values.mp4 (10.02 MB)
16 Different register methods.mp4 (3.27 MB)
17 Working with Desired Value.mp4 (50.96 MB)
19 Working with Mirrored Value.mp4 (36.56 MB)
2 Types of Predictor Implicit Predictor.mp4 (20.61 MB)
21 Understanding predict and mirror.mp4 (23.48 MB)
22 Demonstration.mp4 (53.73 MB)
24 Single Read and Write Transaction.mp4 (30.26 MB)
25 Multiple Read and Write Transaction.mp4 (12.99 MB)
27 Using randomize.mp4 (21.18 MB)
29 Understanding Reset Methods.mp4 (6.99 MB)
3 Types of Predictor Explicit Predictor.mp4 (1.81 MB)
30 Demonstration.mp4 (40.62 MB)
32 Connecting reset methods to DUT.mp4 (15.54 MB)
4 Types of Predictor Passive Predictor.mp4 (8.61 MB)
6 Driver Sequencer Communication.mp4 (37.14 MB)
8 Understanding Design.mp4 (6.15 MB)
9 Adding Driver + Sequencer.mp4 (20.44 MB)
1 Agenda.mp4 (889.74 KB)
10 Peek and Poke P1.mp4 (15.52 MB)
11 Peek and Poke P2.mp4 (4.53 MB)
2 Type of access methods p1 Frontdoor.mp4 (4.37 MB)
3 Type of access methods p2 Backdoor.mp4 (3.93 MB)
4 Frontdoor Demonstration.mp4 (17.35 MB)
6 Fundamentals of Backdoor access.mp4 (6.72 MB)
7 Demonstration.mp4 (53.27 MB)
1 Agenda.mp4 (649.18 KB)
10 Coverage analysis P1.mp4 (37.84 MB)
11 Coverage analysis P2.mp4 (8.84 MB)
12 Coverage analysis P3.mp4 (6 MB)
2 Understanding Design for Explicit Predictor.mp4 (4.75 MB)
3 Building Verification env P1.mp4 (29.52 MB)
4 Building Verification env P2.mp4 (11.97 MB)
5 Building Verification env P3.mp4 (9.35 MB)
6 Building Verification env P4.mp4 (2.23 MB)
7 Testing Code.mp4 (12.47 MB)
1 Agenda.mp4 (1.08 MB)
12 Coverage computation for memory P1.mp4 (4.06 MB)
13 Coverage computation for memory P2.mp4 (21.51 MB)
2 Understanding Design.mp4 (5.35 MB)
3 Building DRV + MON + SCO + AGENT.mp4 (23.64 MB)
4 Building Register model.mp4 (35.07 MB)
5 Adding Register sequence Single Transaction.mp4 (54.18 MB)
6 Adding Register sequence Multiple Transactions.mp4 (10.33 MB)
9 Burst Transactions.mp4 (68.24 MB)
1 Agenda.mp4 (333.31 KB)
2 Understanding Design P1.mp4 (11 MB)
3 Understand Design P2.mp4 (12.11 MB)
4 Building Verification environment P1.mp4 (14.38 MB)
5 Building Verification environment P2.mp4 (29.25 MB)
6 Building Register model P1.mp4 (20.33 MB)
7 Building Register model P2.mp4 (17.45 MB)
8 Adding testbench top.mp4 (5.33 MB)
9 Testing DUT.mp4 (12.38 MB)
10 Components of Register model P2.mp4 (6.71 MB)
11 Components of Register model P3.mp4 (6.78 MB)
13 Typical Learning Path.mp4 (7.44 MB)
14 Understanding different types of registers.mp4 (5.78 MB)
15 Implementation of Register in Verification Environmnet P1.mp4 (48.5 MB)
16 Implementation of Register in Verification Environmnet P2.mp4 (53.63 MB)
17 Alternate way of adding configure function.mp4 (3.25 MB)
18 Summary Configure function.mp4 (4.56 MB)
19 Implementation of Register in Verification Environmnet P3.mp4 (20.76 MB)
2 Agenda.mp4 (6.14 MB)
22 Adding Register with two fields.mp4 (36.86 MB)
24 Adding Register with reserved bits.mp4 (19.39 MB)
26 Different Access Policy P1.mp4 (5.13 MB)
27 Different Access Policy P2.mp4 (55.58 MB)
28 Different Access Policy P3.mp4 (43.54 MB)
29 Different Access Policy P4.mp4 (50.73 MB)
3 Advantage of UVM RAL P1.mp4 (11.98 MB)
31 Adding Memory P1.mp4 (3.69 MB)
32 Adding Memory P2.mp4 (31.41 MB)
4 Advantage of UVM RAL P2.mp4 (7.67 MB)
5 Advantage of UVM RAL P3.mp4 (4.07 MB)
6 Advantage of UVM RAL P4.mp4 (4.76 MB)
7 When to use RAL in Verification environment.mp4 (22.26 MB)
9 Components of Register model P1.mp4 (27.05 MB)
1 Agenda.mp4 (622.66 KB)
2 Adding Register Block P1.mp4 (12.36 MB)
3 Adding Register Block P2.mp4 (18.16 MB)
4 Adding Register Block P3.mp4 (59.01 MB)
1 Agenda.mp4 (3.12 MB)
10 Adapter code with Protocol Specific ports P1.mp4 (23.76 MB)
11 Adapter code with Protocol Specific ports P2.mp4 (4.46 MB)
12 Summary.mp4 (8.02 MB)
2 Usage of adapter.mp4 (2.16 MB)
3 Typical flow.mp4 (2.85 MB)
4 Structure of uvm reg bus op struct.mp4 (3.17 MB)
5 Complete flow.mp4 (7.02 MB)
6 Understanding reg2bus.mp4 (35.07 MB)
7 Understanding bus2reg.mp4 (4.35 MB)
8 Adapter code with native memory ports P1.mp4 (12.6 MB)
9 Adapter code with native memory ports P2.mp4 (14.68 MB)
1 Agenda.mp4 (1.98 MB)
10 Adding Agent.mp4 (2.88 MB)
11 Adding Register Model.mp4 (44.04 MB)
12 Adding env + uvm test top + testbench top.mp4 (15.58 MB)
13 Executing Code.mp4 (13.13 MB)
15 Understanding Desired and Mirrored Values.mp4 (10.02 MB)
16 Different register methods.mp4 (3.27 MB)
17 Working with Desired Value.mp4 (50.96 MB)
19 Working with Mirrored Value.mp4 (36.56 MB)
2 Types of Predictor Implicit Predictor.mp4 (20.61 MB)
21 Understanding predict and mirror.mp4 (23.48 MB)
22 Demonstration.mp4 (53.73 MB)
24 Single Read and Write Transaction.mp4 (30.26 MB)
25 Multiple Read and Write Transaction.mp4 (12.99 MB)
27 Using randomize.mp4 (21.18 MB)
29 Understanding Reset Methods.mp4 (6.99 MB)
3 Types of Predictor Explicit Predictor.mp4 (1.81 MB)
30 Demonstration.mp4 (40.62 MB)
32 Connecting reset methods to DUT.mp4 (15.54 MB)
4 Types of Predictor Passive Predictor.mp4 (8.61 MB)
6 Driver Sequencer Communication.mp4 (37.14 MB)
8 Understanding Design.mp4 (6.15 MB)
9 Adding Driver + Sequencer.mp4 (20.44 MB)
1 Agenda.mp4 (889.74 KB)
10 Peek and Poke P1.mp4 (15.52 MB)
11 Peek and Poke P2.mp4 (4.53 MB)
2 Type of access methods p1 Frontdoor.mp4 (4.37 MB)
3 Type of access methods p2 Backdoor.mp4 (3.93 MB)
4 Frontdoor Demonstration.mp4 (17.35 MB)
6 Fundamentals of Backdoor access.mp4 (6.72 MB)
7 Demonstration.mp4 (53.27 MB)
1 Agenda.mp4 (649.18 KB)
10 Coverage analysis P1.mp4 (37.84 MB)
11 Coverage analysis P2.mp4 (8.84 MB)
12 Coverage analysis P3.mp4 (6 MB)
2 Understanding Design for Explicit Predictor.mp4 (4.75 MB)
3 Building Verification env P1.mp4 (29.52 MB)
4 Building Verification env P2.mp4 (11.97 MB)
5 Building Verification env P3.mp4 (9.35 MB)
6 Building Verification env P4.mp4 (2.23 MB)
7 Testing Code.mp4 (12.47 MB)
1 Agenda.mp4 (1.08 MB)
12 Coverage computation for memory P1.mp4 (4.06 MB)
13 Coverage computation for memory P2.mp4 (21.51 MB)
2 Understanding Design.mp4 (5.35 MB)
3 Building DRV + MON + SCO + AGENT.mp4 (23.64 MB)
4 Building Register model.mp4 (35.07 MB)
5 Adding Register sequence Single Transaction.mp4 (54.18 MB)
6 Adding Register sequence Multiple Transactions.mp4 (10.33 MB)
9 Burst Transactions.mp4 (68.24 MB)
1 Agenda.mp4 (333.31 KB)
2 Understanding Design P1.mp4 (11 MB)
3 Understand Design P2.mp4 (12.11 MB)
4 Building Verification environment P1.mp4 (14.38 MB)
5 Building Verification environment P2.mp4 (29.25 MB)
6 Building Register model P1.mp4 (20.33 MB)
7 Building Register model P2.mp4 (17.45 MB)
8 Adding testbench top.mp4 (5.33 MB)
9 Testing DUT.mp4 (12.38 MB)
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