Digital Ic/Fpga Design P4: Sta && Dc SynThesis

[0dayddl]

Digital Ic/Fpga Design P4: Sta && Dc Synthesis
Published 2/2025
MP4 | Video: h264, 1920x1080 | Audio: AAC, 44.1 KHz
Language: English | Size: 1.86 GB | Duration: 3h 9m​

Static Timing Analysis and DC Synthesis

What you'll learn

Principle of STA

Basics of stander cell library

Characters of clock in STA

Setup/hold timing analysis for same clock

Common used timing constraints

Timing analysis for same clock domain (synchronous path)

Timing analysis for different clock domain (asynchronous path)

Synthesis example using Design Compiler (including whole TCL script)

Requirements

Basic knowledge of digital fundamental

Description

In this chapter I will introduce how to do static timing analysis for digital circuit. And give you're a synthesis example using Design Compiler from Synopsys. Detailed contents:1: Principle of STA;2: Basics of stander cell library;3: Characters of clock in STA;4: Setup/hold timing analysis for same clock;5: Common used timing constraints;6: Timing analysis for same clock domain (synchronous path);7: Timing analysis for different clock domain (asynchronous path);8: Concept of OCV;9: Synthesis example using Design Compiler from Synopsys (including whole TCL script);This is chapter 4 of whole Digital IC and FPGA design course.In the whole course, I will introduce fundamentals of digital IC and FPGA design, with 12+ coding exercises and 3 course projects.Theory part: MOS transistor -> logic cells -> arithmetic data path -> Verilog language -> common used HW function blocks and architecture -> STA -> on-chip-bus(APB/AHB-Lite/AXI4) -> low power design -> DFT -> SOC(MCU level).Function blocks and architecture: FSM, pipeline, arbiter, CDC, sync_fifo, async_fifo, ping-pong, pipeline with control, slide window, pipeline hazard and forward path, systolic.Project: SHA-256 algorithm with simple interface, SHA-256 with APB/AXI interface, 2D DMA controller with APB/AXI interface.After explaining of each HW architecture, I will give you a coding exercise, with reference code. Coding difficulty will begin from several lines to fifty lines, more than 100 lines, then around 200 lines. While the final big project will be 1000+ lines.I suppose these should be essential knowledge and skills you need master to enter this area.I will try my best to explain what-> how-> why and encourage you to do it better in this course.Please browse to my homepage on Udemy to obtain information about each chapter of this course.

Overview

Section 1: Introduction

Lecture 1 Introduction of Static Timing Analysis

Section 2: Principle of STA

Lecture 2 Why need Static Timing Analysis

Lecture 3 Timing and DRC Check Types

Lecture 4 Cell Library and Delay Calculate

Section 3: Timing Analysis for Synchronous Path

Lecture 5 Charactors and Define of Clock in STA

Lecture 6 Terminology for STA

Lecture 7 Setup&&Hold Calculation for Timing Path of Same Clock

Senior undergraduate students of EE or higher,IC design/verification engineers with 0~2 year experience

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